View BR93LC46RF_4933891.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 memory ics 1,024-bit serial electrically erasable prom br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv features ?low power cmos technology ?64 16bit configuration ?2.7v to 5.5v operation ?low power dissipation ?3ma (max.) active current: 5v ?5 m a (max.) standby current: 5v ?auto increment for efficient data dump ?automatic erase-before-write ?hardware and software write protection ?default to write-disabled state at power up ?software instructions for write-enable / disable ?vcc lockout inadvertent write protection ?8-pin sop / 8-pin ssop-b / 8-pin dip packages ?device status signal during write cycle ?ttl-compatible input / output ?100,000 erase / write cycles ?10 years data retention pin assignments pin descriptions 1 2 3 4 8 7 6 5 cs sk di do v cc n.c. n.c. gnd br93lc46 / BR93LC46RF 1 2 3 4 8 7 6 5 n.c. v cc cs sk n.c. gnd do di br93lc46f / br93lc46fv chip select input serial clock input ground not connected not connected power supply start bit, operating code, address, and seria data input serial data output, ready / busy internal status display output function cs sk di do gnd n.c. n.c. v cc pin name overview the br93lc46 series are cmos serial input / output-type memory circuits (eeproms) that can be programmed electrically. each is configured of 64 words 16 bits (1,024 bits), and each word can be accessed individually and data read from it and written to it. operation control is performed using five types of commands. the commands, addresses, and data are input through the di pin under the control of the cs and sk pins. in a write operation, the internal status signal (ready or busy) can be output from the do pin.
2 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv block diagram 16bit 16bit 6bit cs sk di do 6bit command decode control clock generation command register dummy bit address buffer data register power supply voltage detector write disable high voltage generator address decoder r / w amplifier 1,024-bit eeprom array absolute maximum ratings (ta = 25?) parameter symbol limits unit v cc ?0.3 ~ + 6.5 v br93lc46 pd 500 * 1 mw br93lc46f / rf 350 * 2 300 * 3 tstg ?65 ~ + 125 c br93lc46fv topr ?40 ~ + 85 c 0.3 ~ v cc + 0.3 v applied voltage power dissipation storage temperature operating temperature terminal voltage * 1 reduced by 5.0mw for each increase in ta of 1 c over 25 c. * 2 reduced by 3.5mw for each increase in ta of 1 c over 25 c. * 3 reduced by 3.0mw for each increase in ta of 1 c over 25 c. recommended operating conditions (ta = 25?) parameter symbol min. typ. max. unit v cc 5.5 v 2.0 5.5 v v in 0v cc v 2.7 power supply voltage input voltage writing reading
3 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv electrical characteristics for 5v operation (unless otherwise noted, ta = ?40 to + 85?, v cc = 5v 10%) parameter symbol min. typ. max. unit conditions v il ?0.3 0.8 v v ih 2.0 v v ol1 0.4 v i ol = 2.1ma v oh1 2.4 v i oh = ?0.4ma v ol2 0.2 v i ol = 10 m a v oh2 v cc ?0.4 v cc + 0.3 vi oh = ?10 m a i li ?1.0 m av in = 0v ~ v cc i lo ?1.0 m av out = 0v ~ v cc , cs = gnd i cc1 1.5 3 ma i cc2 0.7 1.5 ma i sb 1.0 5 m a 1.0 1.0 cs = sk = di = gnd, do = open v in = v ih / v il , do = open v in = v ih / v il , do = open f = 1mhz, write f = 1mhz, read input low level voltage input high level voltage output low level voltage 1 output high level voltage 1 output low level voltage 2 output high level voltage 2 input leakage current output leakage current operating current standby current operating current dissipation 1 dissipation 2 for 3v operation (unless otherwise noted, ta = ?40 to + 85?, v cc = 3v 10%) parameter symbol min. typ. max. unit conditions v il ?0.3 0.15 v cc v v ih 0.7 v cc v cc + 0.3 v v ol 0.2 v i ol = 10 m a v oh v cc ?0.4 v i oh = ?10 m a i li ?1.0 m av in = 0v ~ v cc i lo ?1.0 m a i cc1 0.5 2 ma i cc2 0.2 1 ma i sb 0.4 3 m a 1.0 1.0 v out = 0v ~ v cc , cs = gnd v in = v ih / v il , do = open v in = v ih / v il , do = open cs = sk = di = gnd, do = open f = 250khz, write f = 250khz, read input low level voltage input high level voltage output low level voltage output high level voltage standby current operating current dissipation 2 operating current dissipation 1 output leakage current input leakage current for 2v operation (unless otherwise noted, ta = ?40 to + 85?, v cc = 2.0v) parameter symbol min. typ. max. unit conditions v il ?0.3 0.15 v cc v v ih 0.7 v cc v cc + 0.3 v v ol 0.2 v i ol = 10 m a v oh v cc ?0.4 v i oh = ?10 m a i li ?1.0 m av in = 0v ~ v cc i lo ?1.0 m a i cc2 0.2 1 ma i sb 0.4 3 m a 1.0 1.0 v out = 0v ~ v cc , cs = 0v v in = v ih / v il , do = open cs = sk = di = 0v, do = open f = 200khz, read input low level voltage input high level voltage output low level voltage output high level voltage input leakage current output leakage current operating current dissipation 2 standby current
4 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv (2) operation timing characteristics for 5v operation (unless otherwise noted, ta = ?40 to + 85?, v cc = 5v 10%) parameter symbol min. typ. max. unit f sk 1mhz t skh 450 ns t skl 450 ns t cs 450 ns t css 50 ns t dis 100 ns t csh 0ns t dih 100 ns t pd1 500 ns t pd0 500 ns t sv 500 ns t df 100 ns t e / w 10ms sk clock frequency sk "h" time cs setup time cs hold time data "1" output delay time data "0" output delay time time from cs to output confirmation time from cs to output high impedance write cycle time sk "l" time cs "l" time di setup time di hold time circuit operation (1) command mode with these ics, commands are not recognized or acted upon until the start bit is received. the start bit is taken as the first ??that is received after the cs pin rises. * 1 after setting of the read command and input of the sk clock, data corre- sponding to the specified address is output, with data corresponding to up- per addresses then output in se- quence. (auto increment function) * 2 when the write or write all addresses command is executed, all data in the selected memory cell is erased auto- matically, and the input data is written to the cell. * 3 these modes are optional modes. please contact rohm for information on operation timing. 1 10 a5 ~ a0 1 00 11xxxx 1 01 a5 ~ a0 d15 ~ d0 1 00 01xxxx d15 ~ d0 1 00 00xxxx 1 11 a5 ~ a0 1 00 10xxxx command read (read) * 1 write enabled (wen) write (write) * 2 write all addresses (wral) * 2 write disabled (wds) erase (erase) * 3 chip erase (eral) * 3 x: either v ih or v il start bit operating code address data
5 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv for low voltage operation (unless otherwise noted, ta = ?40 to + 85?, v cc = 3v 10%) parameter symbol min. typ. max. unit f sk 250 khz t skh 1 m s t skl 1 m s t cs 1 m s t css 200 ns t dis 400 ns t csh 0ns t dih 400 ns t pd1 2 m s t pd0 2 m s t sv 2 m s t df 400 ns t e / w 25ms sk clock frequency sk "h" time sk "l" time cs setup time cs hold time data "1" output delay time data "0" output delay time time from cs to output confirmation time from cs to output high impedance write cycle time cs "l" time di setup time di hold time when reading at low voltage (unless otherwise noted, ta = ?40 to + 85?, v cc = 2.0v) parameter symbol min. typ. max. unit f sk 200 khz t skh 2 m s t skl 2 m s t cs 2 m s t css 400 ns t dis 800 ns t csh 0 ns t dih 800 ns t pd1 4 m s t pd0 4 m s t df 800 ns sk clock frequency sk "h" time sk "l" time cs "l" time cs setup time di setup time cs hold time di hold time data "1" output delay time data "0" output delay time time from cs to output high impedance s not designed for radiative rays.
6 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv (3) timing chart cs sk di do (read) do (write) status valid t df t df t pd1 t pd0 t dih t dis t css t csh t skh t skl ?data is acquired from di in synchronization with the sk rise. ?during a reading operation, data is output from do in synchronization with the sk rise. ?after the completion of each mode, make sure that cs is set to low, to reset the internal circuit, before changing modes. fig. 1 synchronized data timing ?during a writing operation, a status valid (ready or busy) is valid from the time cs is high until time tcs after cs falls fo llowing the input of a write command and before the output of the next command start bit. also, do must be in a high-z state when cs is low.
7 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv cs sk di do ( * 1) ( * 2) d14 d15 d1 d14 d15 0 high z 110 a5 a4 a1 a0 1 2 4 9 10 25 26 d0 ( * 2) address auto increment function: these ics are equipped with an address auto increment function which is effective only duri ng reading operations. with this function, if the sk clock is input following execution of one of the above reading commands, data is read from upper addre sses in succession. cs is held in high state during automatic incrementing. ( * 1) if the first data input following the rise of the start bit cs is "1", the start bit is acknowledged. also, if a "1" is inpu t following several zeroes in succession, the "1" is recognized as the start bit, and subsequent operation commences. this applies also to all commands described subsequent ly. fig. 2 read cycle timing (read) (4) reading (figure 2) when the read command is acknowledged, the data (16 bits) for the input address is output serially. the data is synchronized with the sk rise during a0 acqui- sition and a ??(dummy bit) is output. all further data is output in synchronization with the sk pulse rises. (5) write enable (figure 3) these ics are set to the write disabled state by the in- ternal reset circuit when the power is turned on. therefore, before performing a write command, the write enable command must be executed. when this command is executed, it remains valid until a write disable command is issued or the power supply is cut off. however, read commands can be used in either the write enable or write disable state. (6) write (figure 4) this command writes the input 16-bit data (d15 to d0) to the specified address (a5 to a0). actual writing of the data begins after cs falls (following the 25th clock pulse after the start bit input), and do is in the acquire state. status is not detected if cs = low after the time t e / w . when status is detected (cs = high), no com- mands are accepted while do is low (busy). therefore, no commands should be input during this period. 10011 cs sk di do high z fig. 3 write enable cycle timing
8 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv cs sk di do high z 01 1 a5 a4 a1 a0 d15 d14 d1 d0 1 24 910 25 status t cs ready busy t sv t e / w fig. 4 write cycle timing (write) cs sk di do high z 00 101 d15 d14 d1 d0 12 5 10 25 status t sv ready busy t cs t e / w fig. 5 write all address cycle timing. (wral) (status) after time t cs following the fall of cs, after input of the write command), if cs is set to high, the write execute = busy (low) and the command wait status ready (high) are output. if in the command wait status (status = ready), the next command can be performed within the time t e / w . thus, if data is input via sk and di with cs = high in the t e / w period, erroneous operations may be per- formed. to avoid this, make sure that di = low when cs = high. (caution is especially important when common input ports are used.) this applies to all of the write commands. (7) all address write (figure 5) with this command, the input 16-bit data is written simultaneously to all of the addresses (64 words). rather than writing one word at a time, in succession, data is written all at one time, enabling a write time of t e / w . (8) write disable (figure 6) when the power supply is turned on, the ic enters the write disable status. similarly, when the write disable command is issued, the ic enters the same status. when in this status, all write commands are ignored, but read commands may be executed. in the write enable status, writing begins even if a write command is entered accidentally. to prevent errors of this type, we recommend executing a write disable command after writing has been completed. 1 0000 cs sk di do high z fig. 6 write disable cycle timing (wds)
9 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv a b t e / w write, wral ? read ? fig.7 1 bit 2 bits 6 bits 16 bits start bit operating code address data 1 bit 2 bits 6 bits 16 bits start bit operating code address data cancel can be performed for the entire read mode space cancellation method: cs low a: canceled by setting cs low or v cc off ( * ) b: cannot be canceled by any method. if v cc is set to off during this time, the data in the designated address is not secured. * v cc off (v cc is turned off after cs is set to low) operation notes (1) cancelling modes
10 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv (2) timing in the standby mode as shown in figure 8, during standby, if cs rises when sk is high, the di state may be read on the rising edge. if this happens, and di is high, this is taken to be the start bit, causing a bit error (see point ??in figure 8). make sure all inputs are low during standby or when turning the power supply on or off (see figure 9). (3) precautions when turning power on and off when turning the power supply on and off, make sure cs is set to low (see figure 10). when cs is high, the eeprom enters the active state. to avoid this, make sure cs is set to low (dis- able mode) when turning on the power supply. (when cs is low, all input is cancelled.) when the power supply is turned off, the low power state can continue for a long time because of the capacity of the power supply line. erroneous opera- tions and erroneous writing can occur at such times for the same reasons as described above. to avoid this, make sure cs is set to low before turning off the power supply. to prevent erroneous writing, these ics are equipped with a por (power on reset) circuit, but in order to achieve operation at a low power supply, v cc is set to operate at approximately 1.3v. after the por has been activated, writing is disabled, but if cs is set to high, writing may be enabled because of noise or other fac- tors. however, the por circuit is effective only when the power supply is on, and will not operate when the power is off. also, to prevent erroneous writing at low voltages, these ics are equipped with a built-in circuit (v cc -lock- out circuit) which resets the write command if v cc drops to approximately 2v or lower (typ.) ( * ). * with the br93lc46a, the circuit is tripped at approximately 3v or less (typ). (4) clock (sk) rise conditions if the clock pin (sk) signal of the br93lc46 has a long rise time (tr) and if noise on the signal line exceeds a certain level, erroneous operation can occur due to erroneous counts in the clock. to prevent this, a schmitt trigger is built into the sk input of the br93lc46. the hysteresis amplitude of this circuit is set to approximately 0.2v, so if the noise exceeds the sk input, the noise amplitude should be set to 0.2v p-p or lower. furthermore, rises and falls in the clock input should be accelerated as much as possible. (5) power supply noise the br93lc46 discharge high volumes of high voltage when a write is completed. the power supply may fluc- tuate at such times. therefore, make sure a capacitor of 1000pf or greater is connected between v cc (pin 8) and gnd (pin 5). sk cs di ab 01 point a: start bit position during erroneous operation point b: timing during normal operation fig. 8 erroneous operation timing sk cs di 01 b fig. 9 normal operation timing good example bad example gnd + 5v gnd + 5v v cc cs here, the cs pin is pulled up to v cc . in this case, cs is high (active state). please be aware that the eeprom may perform erroneous operations or write erroneous data because of noise or other factors. please be aware that this can occur even if the cs input is high-z. in this case, cs is low when the power supply is turned on or off. fig. 10 (bad example) (good example)
11 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv (6) connecting di and do directly the br93lc46 have an independent input pin (di) and output pin (do). these are treated as individual signals on the timing chart but can be controlled through one control line. control can be initiated on a single control line by inserting a resistor r. 1) data collision between the m -com output and the do output within the input and output timing of the br93lc46 the drive from the m -com output to the di input and a signal output from the do output can be emitted at the same time. this happens only for the 1 clock cycle (a dummy bit ??is output to the do pin) which acquires the a0 address data during a read cycle. when the address data a0 = 1, the m -com output becomes a direct current source for the do pin. the resistor r is the only resistance which limits this current. therefore, a resistor with a value which satisfies the m -com and the br93lc46 current capacity is required. when using a single control line, when a dummy bit ??is out- put to the do, the m -com i / o address data a0 is also output. therefore, the dummy bit cannot be detected. 2) feedback to the di input from the do output data is output from the do pin and then feeds back into the di input through the resistor r. this happens when: ?do data is output during a read operation ?a ready / busy signal is output during write or wral operation such feedback does not cause problems in the basic operation of the br93lc46. the m -com input level must be adequately maintained for the voltage drop at r which is caused by the total input leakage current for the m -com and the br93lc- 46. in the state in which sk is input, when the ready / busy function is used, make sure that cs is dropped to low within four clock pulses of the output of the ready signal high and the standby mode is restored. for input after the fifth clock pulse, the ready high will be taken as the start bit and wds or some other mode will be activated, depending on the di state. m com r di do br93lc46 io port fig. 11 common connections for the di and do control line
12 memory ics br93lc46 / br93lc46f / BR93LC46RF / br93lc46fv external dimension (units: mm) br93lc46 br93lc46f / rf dip8 sop8 ssop-b8 br93lc46fv 0.5 0.1 3.2 0.2 3.4 0.3 85 14 9.3 0.3 6.5 0.3 0.3 0.1 0.51min. 2.54 0 ~ 15 7.62 0.4 0.1 1.27 0.15 0.3min. 0.15 0.1 0.11 6.2 0.3 4.4 0.2 5.0 0.2 85 4 1 1.5 0.1 0.1 0.22 0.1 0.65 0.3min. 5 4 8 1 6.4 0.3 4.4 0.2 3.0 0.2 1.15 0.1 0.15 0.1 0.1 (0.52)

▲Up To Search▲

Price & Availability of BR93LC46RF

	To Download BR93LC46RF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .